The present invention relates to a procedure for testing electronic circuit devices of the type used to synchronize or latch asynchronous signals. More particularly, a procedure is defined the practice of which both identifies devices having fundamental metastability problems and estimates the mean time between failure to resolve (MTBFR) for devices which satisfy a set of threshold conditions.
In the electronic devices, metastability describes the state of a synchronizing device when its output is in neither a logical one nor a logical zero state. It is normally a transient phenomenon, and has been the subject of various publications extending back into the early 1970 time period. For example, concepts of metastability are discussed in the article by authors Chaney et al. entitled "Anomalous Behavior of Synchronizer and Arbiter Circuits" which appeared in the IEEE Transactions on Computers, pages 421-422, in April of 1973. The effects of noise on metastability in cross-coupled inverters was the subject of an article by Veendrick entitled "The Behavior of Flip-Flops Used as Synchronizers and Prediction of Their Failure Rate" as appeared in the IEEE Journal of Solid State Circuits, Vol. SC-15, No. 2, pages 169-176, in April of 1980, and was also considered in the article authored by Kinniment et al. entitled "Synchronization and Arbitration Circuits in Digital Systems" which appeared in the proceedings of the Institute of Electronical Engineers (England), Vol. 123, pages 961-966, in October of 1976. The susceptibility of integrated circuit synchronizing devices employing Schottky semiconductors to oscillate when subject to metastable conditions is discussed in a publication authored by Goodrich, entitled "Pinpointing Metastable Problems Leads to More Reliable Designs" which appeared in Communications Systems Equipment Design, pages 33-35, in February of 1985, and in the paper by Chaney et al. entitled "Beware of the Synchronizer" published in the Proceedings of COMPCON-72, IEEE Computer Society Conference, pages 317-319 in 1972. A circuit arrangement for reducing metastable states and synchronizing elements is described in relatively recent U.S. Pat. No. 4,575,644, where the complementary output of the latching flip-flop is influenced by the injection of a high frequency but low amplitude pertubation signal.
In contemporary designs the metastable state is most often encountered when the set-up and hold times of D-type latches are violated, e.g. by a lack of synchronizism between the latch signal and the data signal.
Notwithstanding the contribution of the prior art to the understanding of metastability as a problem, there remains a need for a practical procedure by which a synchronizing device can be evaluated for susceptibility to metastable conditions, and an extension of such procedure to the actual estimation of the meantime between failure of a fundamentally suitable device to resolve a data signal in the context of its routine use.